Projects
Mixed Signal ASIC for Matrix-Vector Multiplication
June 2025 – November 2025
Tags: ASIC, Signal Processing, Simulation, ASIC Layout
Repository · Custom-made Schematic Optimizer
- Computes matrix–vector products with programmable resistors (weights), DAC-driven inputs, TIAs, and SAR ADCs.
- Defined SAR ADC architecture and conversion sequencing to digitize outputs Y1…Yn.
- Designed trans-impedance amplifiers (TIAs) to sense and condition MVM currents for accurate readout.
- Built voltage-source DACs to drive input vector voltages representing column entries −X1…−Xm.
- Implemented programmable-resistor DACs to encode row entries per the system architecture.
- Developed digital control and interface logic supporting AXI interface to drive biases, orchestrate conversions, and read back results.
- Surveyed IEEE literature and alternative analog MVM implementations to guide design trade-offs.
- Developed a custom tool that optimizes xschem schematics by running automated ngspice simulations and parameter sweeps.
- Designed SAR ADC blocks and low-noise, high-bandwidth op-amps for TIA front-ends and buffering stages.
Custom 50V ESC PCBA for Micromobility Vehicles with BLDC Motors
May 2025 – September 2025
Tags: PCBA, PCB
Repository
- Designed a custom 4-layer PCB for a 50V brushless motor electronic speed controller (ESC) targeting micromobility vehicles.
- Created the schematic and PCB layout in KiCad, ensuring signal integrity and thermal management for high-current paths.
- Selected components and created a bill of materials (BOM) that reduced costs by over 30% while meeting performance requirements.
- Increased availability of user-accessible GPIO by 10% compared to existing ESCs on the market.
FPGA Implementation of a configurable digital 512x512 Matrix-Vector Multiplier targeting Xilinx Series 7 FPGAs
July 2025 – August 2025
Tags: RTL, FPGA, RTL Verification, Python, Signal Processing
Repository
- Designed a highly configurable digital matrix-vector multiplier (MVM) in Verilog, capable of handling 512x512 matrices with 8-bit integers.
- Implemented the design to utilize Xilinx Series 7 FPGA DSP slices for efficient multiplication and addition operations, utilizing bit-packing techniques and ternary adders to maximize resource efficiency.
- Developed a Python-based testbench using cocotb to perform exhaustive verification of separate modules and the overall MVM system, achieving 100% functional coverage across all configurations.
- Achieved a clock frequency of up to 300 MHz on a Xilinx Pynq-Z1 board, with throughput of 38.4 GOPS.
- Obtained resource usage of approximately 95% of DSP slices and 70% of LUTs on the FPGA for the full 512x512 configuration.
- Utilized various implementation strategies, including disabling synthesis optimizations and floorplanning, to meet timing constraints and optimize performance.
ASIC & FPGA Implementation on a Torus NoC based on HopliteRT
May 2025 – August 2025
Tags: Networks-on-Chip, RTL, ASIC, FPGA, RTL Verification, Python
Repository · HopliteRT
- Implemented a 4x4 2D Torus Network-on-Chip using the HopliteRT router architecture, supporting virtual channels and deadlock-free routing.
- Designed and verified the NoC (including router, switch, and a client interface components) in SystemVerilog, simulating with Verilator and to ensure correct functionality and performance.
- Achieved timing closure on the ASIC design targeting the TSMC 65nm node using Synopsys Design Compiler and Innovus, meeting the performance and area requirements.
- Successfully synthesized and implemented the NoC on a Xilinx Artix-7 FPGA, achieving a maximum clock frequency of 200 MHz.
- Developed a script for custom placement of the NoC routers on the FPGA and floorplanning to optimize routing and minimize latency.
3D Torus NoC Simulator in Booksim
June 2025 – August 2025
Tags: Networks-on-Chip, Booksim, Simulation, Python
Repository
Project Report
- Extended Booksim2 to support a 3D Torus with bidirectional Z-dimension meshing for reducing bottlenecks from through-silicon vias (TSVs).
- Implemented elevator-first deterministic routing, ensuring livelock and deadlock freedom while prioritizing Z > Y > X traversal.
- Developed Python tooling for flexible elevator mapping: users can specify elevator coordinates via CSV, visualize mappings, and customize nearest-elevator selection functions.
- Modeled TSVs with realistic multi-cycle latency penalties and integrated them into Booksim’s credit-based flow control system.
- Explored elevator placement patterns (diagonal, checkerboard, sub-tiling) and quantified performance tradeoffs across throughput, latency, and injection rate.
- Demonstrated that bidirectional Z-meshing can nearly double sustainable throughput with only ~33% area overhead, with non-linear gains depending on elevator density.
SPI-connected PWM Generator
April 2025 – May 2025
Tags: RTL, ASIC, Tapeout, RTL Verification, Python
Repository · GDSII View
- Designed an SPI‑controlled PWM with adjustable frequency and duty cycles for 8 outputs, 2 frequency generators, and 4 channels.
- Implemented the design in RTL using Verilog, targeting a 130nm open source process node based on the IHP130 PDK.
- Verified functionality through extensive simulation and formal verification methods.
- Prepared design for tapeout, including GDSII generation and DRC/LVS checks.
Strivonix Main PCBA and Firmware
January 2025 – March 2025
Tags: Firmware, C, IoT, PCB, PCBA, ESPIDF
Strivonix Website
- Led the design and testing of a portable massage device's 4-layer PCB, exceeding the required targets and reducing BOM cost by over 30%.
- Built ESP32-S3 firmware using ESP-IDF with FreeRTOS, utilizing software FSMs for peripheral interactions, achieving 95% accuracy for sensor readings using adaptively tuned Kalman filtering.
- Implemented BLE drivers for the device to enable user-defined protocols that are saved in non-volatile memory (NVS).
- Integrated OTA update functionality to enable remote firmware updates, improving maintainability and user experience.
- Wrote comprehensive documentation for the PCB design and firmware architecture to facilitate future development and maintenance.
- Conducted extensive testing and validation of the PCB and firmware to ensure reliability and performance under various operating conditions.
Custom 8-bit Computer Tapeout
September 2024 – December 2024
Tags: RTL, RTL Verification, Python, Tapeout, ASIC
Repository · GDSII View
CPU Datasheet
- Architected custom 8-bit ISA CPU with 16 instructions to balance datapath simplicity and opcode density.
- Designed and verified pipelined ALU and register file blocks in Verilog, simulated with Verilator and cocotb.
- Integrated modules from multiple teams to produce tapeout-ready GDS with >20% area savings.
- Validated timing with post-layout netlists and RC extraction to ensure functional accuracy.
- Developed an on-chip programmer to flash programs and data into the RAM by communicating with an external MCU.
- Broke instructions down into microinstructions to be carried out every CPU cycle, enabling the utilization of a single common bus and more complex instructions such as adding from the RAM.
- Developed cocotb test suites for individual modules as well as complete integration tests.
Dino Game ASIC
January 2025 – March 2025
Tags: RTL, RTL Verification, Verilator, Tapeout, FPGA, ASIC
Repository · GDSII View
- Designed and FPGA-tested a 160×200 μm Dino Game ASIC with VGA output, submitted for tapeout via TinyTapeout.
- Generated VGA output in real-time (“raced the beam”) to avoid frame buffer memory overhead due to ASIC size limits.
- Architechted a custom graphics module with sprite rendering, collision detection, and game state management.
- Created an elegant way for implementing different colour palettes that are switched based on the game state using only combinational logic.
- Implemented a linear feedback shift register to generate random numbers and a basic physics engine for player physics.
- Developed an autonomous controller in Verilog to play the game when no controller is detected on startup.
- Developed VGA emulator in C++ using SDL2 and Verilat or to simulate chip input/output and test design in real time.
Wearable Telehealth Device
August 2022 – January 2023
Tags: C++, MATLAB, Signal Processing, IoT
- Built a WiFi-enabled wearable using an ESP8266 SoC and multiple I2C sensors for biometric monitoring.
- Implemented ECG signal processing in MATLAB, achieving >95% arrhythmia classification accuracy.
- Created mobile dashboard with Blynk API and ThingSpeak for cloud monitoring and alerts.
